A successive approximation register (SAR) analog to digital converter (ADC) is often employed in electronic systems to convert an analog signal into a digital representation of the analog signal via a charge scaling circuit that performs a binary search algorithm. The charge scaling circuit generally includes an array of capacitors that is employed to perform the binary search algorithm. However, gain error is often associated with an SAR ADC (e.g., as a result of the binary search algorithm performed by the charge scaling circuit). To compensate for the gain error, a gain calibration process can be employed in connection with the SAR ADC. The gain calibration process is generally performed in the digital domain. For example, a conventional gain adjustment process generally involves a digital multiplier. However, employing a digital multiplier for gain calibration often consumes a large amount of power. Moreover, performing a gain calibration process in the digital domain often results in an increased number of bits for the digital representation of the analog signal, quantization noise and/or decreased performance of the SAR ADC.
The above-described description is merely intended to provide a contextual overview of current SAR ADC systems and is not intended to be exhaustive.